A semiconductor device having a multilayer substrate is disclosed in which a plurality of connecting terminals to which bumps for connection of an LSI chip are fixed are exposed on one outermost layer of the multi layer substrate and solder balls are fixed over metal pads on the other outermost layer to make up a ball grid array (BGA) structure for connection to a motherboard (for example, see Japanese Unexamined Patent Publication No. 2006-73622).
In recent years, in the category of multi-pin semiconductor devices (semiconductor packages), demand for smaller semiconductor chips (shrinkage in size) has been growing for the purpose of cost reduction. This demand is based on the idea that the number of semiconductor chips obtained from a single wafer should be increased by shrinkage in the size of each semiconductor chip (hereinafter called simply “chip”) in order to reduce the cost of multi-pin semiconductor devices.
When priority is given to the multi-pin structure or package size, the BGA (ball grid array) substrate type is selected rather than the lead frame type. In this case, the wiring substrate used here is often a multilayer substrate because of the multi-pin structure. In addition, in the case of multi-pin semiconductor devices, package size depends on the number of pins, so if the chip is shrunk and the number of pins remains unchanged, the interval between pads (pad pitch) should be smaller. This may raise a problem that wirings cannot pass between pads.
In other words, for a multi-pin semiconductor device, chip shrinkage may pose a problem that the pad pitch is too small for wirings to pass between pads.
On the other hand, if the number of pads is increased due to the multi-pin structure and the number of layers of the multilayer substrate is unchanged, the problem may be somewhat relieved by area arrangement (central arrangement) of pads. However, if that is the case, signal wirings to be coupled to signal pads located on the periphery of the main surface of the chip must be drawn inside (toward the center of the chip) and coupled via through holes to another layer and drawn out from the other layer.
Generally, in a semiconductor chip with a larger number of pads, a multilayer wiring substrate is used and area arrangement of pads is adopted. For example, in some multilayer wiring substrates, a total of six wiring layers, three above the core layer and three below it, are formed by a build-up technique or the like and area arrangement of chip pads is also adopted.
However, in the case of multi-pin semiconductor devices, since core power supply bonding electrodes are densely arranged near the chip center, it is not easy to provide space for through holes for electrical coupling to the signal wirings drawn inside in the multilayer wiring substrate.
Therefore, for the multi-pin structure, the number of layers of the multilayer wiring substrate must be increased to arrange wirings properly. This would lead to rise in semiconductor device cost.
Furthermore, when the chip size is reduced, the pad pitch should be decreased, maybe making it difficult for wirings to pass between pads as mentioned above. Thus the problem here is that area arrangement of pads is impossible. On the other hand, though the use of the redistribution technique makes it possible to adopt area arrangement of pads, it involves difficulty in design and necessitates a chip cost increase. Since a rise in the chip cost leads to a rise in the semiconductor device cost, it is not a good solution.
The BGA semiconductor device described in the above patent document also has a problem that if the number of pins is to be increased, the number of wiring layers of the multilayer substrate must be increased, leading to a rise in the semiconductor device cost.
The present invention has been made in view of the above problem and an object thereof is to provide a technique which reduces the cost of multi-pin semiconductor devices.
Another object of the invention is to provide a technique which enables area arrangement of pads in a semiconductor device with a shrunk chip.
The above and further objects and novel features of the invention will more fully appear from the following detailed description in this specification and the accompanying drawings.
Typical aspects of the present invention which are disclosed herein are briefly outlined below.
According to one aspect of the present invention, a semiconductor device which uses a multilayer wiring substrate having an upper surface and a lower surface opposite to the upper surface with a semiconductor chip flip-chip mounted on the upper surface includes the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface, the multilayer wiring substrate in which a plurality of bonding electrodes are formed in a plurality of rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential (power supply and GND) bonding electrodes are formed in a second region inside the first region, and a plurality of external terminals provided on the lower surface of the multilayer wiring substrate. Here, a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
According to another aspect of the invention, a semiconductor device which uses a multilayer wiring substrate having an upper surface and a lower surface opposite to the upper surface with a semiconductor chip flip-chip mounted on the upper surface includes the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface, the multilayer wiring substrate in which a plurality of bonding electrodes are formed in two rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential (power supply and GND) bonding electrodes are formed in a second region inside the first region, and a plurality of external terminals provided on the lower surface of the multilayer wiring substrate. Here, a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
The advantageous effect achieved by preferred embodiments of the invention is briefly outlined below.
In a multi-pin semiconductor device, the chip can be shrunk without the need for an increase in the number of layers in its multilayer wiring substrate, so that the cost of the semiconductor device can be reduced.
In a multi-pin semiconductor device with a shrunk chip, area arrangement of semiconductor chip pads is possible.